Design of Cost-Efficient Interconnect Processing Units

Design of Cost-Efficient Interconnect Processing Units

Spidergon STNoC

by Marcello Coppola
4/5

Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of l.

First published
2020
Publishers
Taylor & Francis Group
Language
English

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